
Table 3-22:
R
Clock Generation
Clock Synthesizer 1 Frequency Output for Multiplier/Divider Values with a 10 MHz Input Clock (Continued)
Multiplier Input Selection
(hex)
M8 M[7:0]
VCO Lock
Frequency Range
(MHz)
Output
Frequency
(MHz) with
Divisor = 1
N[1:0]=00b
Output
Frequency
(MHz) with
Divisor = 2
N[1:0]=01b
Output
Frequency (MHz)
with Divisor = 4
N[1:0]=10b
Output
Frequency
(MHz) with
Divisor = 8
N[1:0]=11b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
35
36
37
38
39
3A
3B
3C
3D
3E
3F
40
41
42
43
44
45
46
0x47 – 0xFF
0x00 – 0xFF
530
540
550
560
570
580
590
600
610
620
630
640
650
660
670
680
690
700
Will not LOCK
530
540
550
560
570
580
590
600
610
620
630
640
650
660
670
680
690
700
N/A
265
270
275
280
285
290
295
300
305
310
315
320
325
330
335
340
345
350
N/A
132.5
135
137.5
140
142.5
145
147.5
150
152.5
155
157.5
160
162.5
165
167.5
170
172.5
175
N/A
66.25
67.5
68.75
70
71.25
72.5
73.75
75
76.25
77.5
78.75
80
81.25
82.5
83.75
85
86.25
87.5
N/A
Virtex-5 FPGA ML555 Development Kit
UG201 (v1.4) March 10, 2008
65